FIG. 1 shows the array architecture of a programmable EEPROM memory, based on a matrix of rows and columns. Each row and each column correspond to a plurality of word lines 101, 102, . . . , 10n, and a plurality of bit lines 201, 202, . . . , 20n, (bits are accessible at 2n bits per word) respectively. An exemplary memory cell 30 is located on each word line 10 and bit line 20 intersection. The memory cell 30 is composed of a select transistor 31 and a floating gate transistor 32 connected in series. The gate of the cell select transistor 31 is connected to the word line 10, its drain to the bit line 20, and its source to the drain of the floating gate transistor 32. A floating gate transistor source 34 is connected to ground via source line 35, and the floating gate transistor's gate 36 may be logically connected to a Vref line 40 when enabled by a word select device 11.
Data storage in a floating gate transistor is obtained by varying electrical charge that exists on the floating gate. To obtain a logical l value (erased state), electrons must be injected into the floating gate, which increases the threshold voltage of the floating gate transistor 32. To obtain a logical 0 value (written state), electrons must be extracted from the floating gate, which decreases the threshold voltage of the floating gate transistor 32. A mechanism referred to as Fowler Nordheim Tunneling is used for both erase and program operations on an EEPROM memory. This mechanism is very slow (in the millisecond range) and requires a high voltage source Vpp that is generated by a circuit within the EEPROM memory chip. The Vref line 40 is driven to Vpp during an erase operation and grounded during a write operation. The bit line 20 is left floating during an erase operation and connected to Vpp during a write operation.
Erasing a cell is obtained by applying a high voltage Vpp on the gate 36 of the floating gate transistor 32 (via word select device 11 and Vref line 40), and ground to the floating gate transistor's source 34 (by grounding source lines 35). To write the memory cell 30, Vpp must be applied to the drain of the floating gate transistor 32 (via bit line 20 and cell select transistor 31), the floating gate transistor's gate 36 must be grounded (via word select device 11 and Vref line 40), and the floating gate transistor's source 34 is left floating (by floating source lines 35).
If memory cells 30 share the same Vref line 40, multiple memory cells may be grouped into words and may be erased in parallel. Also, each bit (memory cell) may be written independently by driving its corresponding bit line 20 to Vpp.
Word programming is obtained in two steps. First the word is erased and all of the erased bits are set to a logic 1 value after erase. Secondly, all of the necessary bits in the word are written at the same time, changing all bits to a logic 0 value in order to program the targeted word data.
With reference to FIG. 1, depending on the threshold voltage (Vth) of the floating gate transistor 32, each memory cell 30 will be conducting or not conducting current. If the threshold voltage Vth is higher than the reference voltage Vref, the memory cell 30 is OFF. If Vth is lower than Vref, the memory cell 30 is ON. A threshold voltage Vth may be adjusted by injecting or removing electrons from the floating gate of each floating gate transistor 32 during a memory cell 30 or word programming operation. During an erase operation, electrons are injected into the floating gate resulting in a high threshold voltage value Vthhigh. During a write operation, electrons are removed from the floating gate, resulting in a low threshold voltage Vthlow. The difference between the high Vthhigh and the low Vthlow is referred to as a program window. The reference voltage value normally applied to the gate of a memory cell 30 during a read operation is between Vthhigh and Vthlow. Due to a possible charge loss from the floating gate, after for example several years, a wide program window is desirable to prevent possible data loss.
The data retention characteristics of each memory cell 30 will depend on a capability of the memory cell 30 to reliably maintain voltage thresholds over time, due to an intrinsic floating gate charge loss. In addition, characteristics of a memory cell 30 may change after several erase and write cycles, resulting from a negative charge trapping phenomenon. These technical characteristics of the memory cell 30 make it difficult to guarantee an acceptable data retention capability.
Therefore, it is desirable to have a program window that is as wide as possible to compensate for characteristics of a programmable memory cell that may affect the integrity of data stored within a memory cell.